1. Field of the Invention
The invention relates generally to a method of testing semiconductor chips, and more particularly, to a test circuit performing a scan test method for verifying electrical and functional characteristics of a System-on-a-Chip (SOC).
A claim of priority is made to Korean Patent Application No. 10-2004-0006463, filed on Jan. 31, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
A test using a scan based Automatic Test Pattern Generation (ATPG) method is performed by connecting a test circuit created by the ATPG method to another circuit and scan-testing the resulting circuit. A scan based ATPG test enables verification of defects in circuits upon product development, thus enabling selection and distribution of products satisfying a particular specification in their electrical and functional characteristics. Since the scan based ATPG test can be automated using an Electronic Design Automation (EDA) tool, this test method is used for the evaluation of most SOCs.
The main factors determining the cost for a scan based ATPG test include the number of scan chains, the number of scan pins, the length of a scan, the volume of scan test data, etc. Considering the above factors, an effective method for reducing test costs will reduce the length of a scan by allowing it to utilize a larger number of scan chains while using a smaller number of scan pins. This approach is intended to reduce a volume of test data and a test time.
The following is an illustration showing a test time associated with a scan based ATPG test. Assume that a SOC device uses 1000 flip flops. The test time for the device must be at least as many clock cycles as the number of flip flops in the device divided by an integer number of scan chains “n” in Automated Test Equipment (ATE) used to perform the test. For example, if the ATE supports three scan chains, the test time must be greater than
  334  ⁢          ⁢  clock  ⁢          ⁢  cycles  ⁢          ⁢            (              1000                  number_of          ⁢          _scan          ⁢          _chains                    )        .  Accordingly, to perform a pattern set operation, at least 335 (334+1) clock cycles are required. 334 clock cycles are used for shift operations and one clock cycle is used for a capture operation. In order to achieve fault coverage above 95%, a total 3,350,000 nanoseconds (ns) are required according to the following equation 1 if 1000 test pattern sets are required and a period of a test clock is 10 ns.Test time=1000(test pattern sets)*335(clock cycles)*10(ns)=3,350,000(ns)  (1)
The amount of test time required by the above method is excessive and hence a method requiring less test time is desired.
FIG. 1 is a diagram showing an example of a conventional scan based ATPG structure.
Referring to FIG. 1, the conventional scan based ATPG structure comprises first through forth scan chains SCAN CHAIN #1 through SCAN CHAIN #4 and eight scan pins, including four scan input pins SCAN-IN and four scan output pins SCAN-OUT. Each scan chain is connected to a scan input pin SCAN-IN and a scan output pin SCAN-OUT. A symbol X shown in third and fourth scan chains SCAN CHAIN #3 and SCAN CHAIN #4 indicates that a certain logic value included in the scan chain is an unknown value.
Testing a highly integrated device such as a SOC using the conventional ATPG structure shown in FIG. 1 requires verification of an enormous amount of test data compared with testing general semiconductor devices. Because the ATE has a limited memory capacity, this causes a significant increase in test costs.
FIG. 2 is a diagram showing a conventional Illinois Scan architecture.
Referring to FIG. 2, the Illinois Scan architecture, as an enhancement of the conventional ATPG structure shown in FIG. 1, comprises first through fourth scan chains SCAN CHAIN #1 through SCAN CHAIN #4, a scan input pin SCAN-IN and four scan output pins SCAN-OUT. The first through fourth scan chains SCAN CHAIN #1 through SCAN CHAIN #4 share a scan input pin SCAN-IN and are respectively connected to the four scan output pins SCAN-OUT. A symbol X shown in third and fourth scan chains SCAN CHAIN #3 and SCAN CHAIN #4 indicates that a certain logic value included in the scan chain is an unknown value.
Since according to the Illinois Scan architecture, all scan chains share one scan input pin SCAN-IN, a total input volume of test data is reduced but a volume of scan output data is the same as in the conventional technique.
FIG. 3 is a diagram showing a scan based ATPG structure as an enhancement of the conventional Illinois Scan architecture shown in FIG. 2.
Referring to FIG. 3, a scan based ATPG structure comprises a scan input pin SCAN-IN, first through fourth scan chains SCAN CHAIN #1 through SCAN CHAIN #4, first through third XOR gates XOR #1, XOR #2, and XOR #3, and a scan output pin SCAN-OUT.
First through third XOR gates XOR #1, XOR #2, and XOR #3 are used to transfer output data from the first through fourth scan chains SCAN CHAIN #1 through SCAN CHAIN #4 to the scan output pin SCAN-OUT, thus substantially compressing the output data of first through fourth scan chains SCAN CHAIN #1 through SCAN CHAIN #4.
First XOR gate XOR #1 receives outputs from scan chains SCAN CHAIN #1 and SCAN CHAIN #2 and second XOR gate XOR #2 receives outputs from scan chains SCAN CHAIN #3 and SCAN CHAIN #4. Third XOR gate XOR #3 receives outputs from first XOR gate XOR #1 and second XOR gate XOR #2. Each XOR gate computes an Exclusive OR function on its inputs and outputs a result of the Exclusive OR function.
Where a conventional scan based ATPG structure is used, an error in a second cycle of second scan chain SCAN CHAIN #2 results in a predetermined signal indicating the error being output through scan output pin SCAN-OUT. Therefore, it is possible to determine whether an error has occurred according to the predetermined signal and perform circuit design modification.
However, where an error is generated in a second cycle of second scan chain SCAN CHAIN #2 and simultaneously an unknown value (hereinafter, referred to as X) exists in a second cycle of the third scan chain SCAN CHAIN #3, a problem arises. In this case, since the output of XOR gate XOR #3 in the second cycle always has unknown value X, the scan output pin SCAN-OUT always outputs unknown value X in the second cycle. Accordingly, in the second cycle, the generation of an error cannot be verified. Cases where unknown value X is generated include a case where a flip flop is un-initialized, a case where a simulation model is a black box, and a case where bus contention causes data collision in buses.
As described above, it is impossible to detect an error in the above cases when using the enhanced scan based ATPG structure shown in FIG. 3.
To effectively address the above-mentioned problems, two approaches have been proposed. A first approach is to prevent unknown value X from being generated. However, this approach has problems in that it creates design/implementation overhead and it requires further implementations and verifications anytime the design is revised. A second approach is to prevent unknown value X from being transferred to a following stage.